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Dr. V Thrimurthulu
Designation Professor
Years of Experience 28
Department CSE
Email Id thrimurthulu.v@mlrit.ac.in
JNTUH Unique Id 3056-240125-155143
Areas of Specialization • Digital Image processing • Wireless cellular & computer Networks • Internet of Things • Antenna & wave Propagation
UG Degree AMIETE ECE
PG Degree M.E. MRE
Ph.D Ph.D. ECE, Wireless Cellular Communication
Joining Date 19-01-2024
Nature of Association Regular

Dr. V Thrimurthulu

Papers Published

Research Articles

  1. “Modern Approach of Detecting Permanent Faults for Multipurpose Processor Design of NOC Relevance’s” in The International journal of analytical and experimental modal analysis (IJAEMA) ISSN NO: 0886-9367, Volume XI, Issue VIII, Page No: 1366-1376, August/2019.
  2. “Design and Implementation of High-Speed Hybrid Adder with Reverse Carry Propagate Adder” in The International journal of analytical and experimental modal analysis (IJAEMA) ISSN NO: 0886-9367, Volume XI, Issue VIII, Page No:1591-1598, August/2019.
  3. “A Novel Reversible Decoder for Design and Synthesis of Combinational Circuits” in Journal of Emerging Technologies and Innovative Research (JETIR) ISSN-2349-5162, Volume 6, Issue 6, page no 627-631, June 2019.
  4. “Design of High Performance Pulse Generator to Perform Automatic Test in VLSI Circuits” in i-manager’s Journal on Electronics Engineering (JEE), ISSN: 2229 – 7286, Vol. 9, No. 3, page 26-31, March – May 2019.
  5. “Interference Mitigation Techniques for Advanced Cellular Communications using MIMO Based Smart Antenna Beam forming” in International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-8 Issue-2S December, 2018.
  6. “An Efficient ARX-Based Cryptography Using SCP Processor” in International Journal for Innovative Engineering and Management Research ISSN NO:2456-5083, Volume 7, Issue 12, Pages:109-114, November/2018.
  7. “High Data Rate in Cooperative Massive MIMO in Cellular System Using Genetic Algorithm and Simulated Annealing” in International Journal of Research in Electronics and Computer Engineering (IJRECE), ISSN: 2393-9028 (PRINT) | ISSN: 2348-2281 (Online), Vol. 6 Issue 4, Pages:293-297, October- December 2018.
  8. “Error Correction Orthogonal Latin Square Code for Various Fault Protection” published in International Journal of Research ISSN NO:2236-6124, Volume 7, Issue XI, Pages:197-202, November 2018.
  9. “Biometric Recognition System through Dorsal Hand Veins” published in International journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.07, Issue.07, Pages:1450-1455, July-2018.
  10. “Medical Image Fusion Based on Quality Assessment Metrics” published in International Journal of Innovative Research and Advanced Studies (IJIRAS), ISSN: 2394-4404, Volume 5 Issue 8, Pages:276-281, August 2018.
  11. “Digital Image watermarking and Encryption using Public Key cryptosystem” published in International Journal of Emerging Technologies and Innovative Research (IJETIR), ISSN: 2349-5162, Volume 5, Issue 9, Pages:607-612, September 2018.
  12. “Segmented B-RAM Based Multiport Memory for Field Programmable Gate Array” published in International Journal of Emerging Technologies and Innovative Research (IJETIR), ISSN: 2349-5162, Volume 5, Issue 9, Pages:607-612, September 2018.
  13. “Deep Learning Accelerator Unit with High Efficiency On FPGA” published in International Journal of Research (IJR), ISSN NO:2227-524X, Volume 7, Issue XI, Pages:215-222, November 2018.
  14. “Investigation on Interference Mitigation Schemes for Next Generation Cellular Communications” in International Journal of Engineering & technology (IJET), ISSN: 2321:5984, Volume 7, Issue 2.20, Special Issue on Innovative Research in Science and Technology at Vijnan Foundation for Science, Technology, and Research, Pages:230-35, April 2018.
  15. “FPGA Implementation of Self Checking Adder Based Viterbi Algorithm Architecture” published in International Journal of Research (IJR), ISSN NO:2236-6124, Volume 7, Issue XI, Pages:598-606, November 2018.
  16. “Design and Analysis of High speed reversible Parallel Prefix Adders” published in International Journal of Research (IJR), ISSN NO:2236-6124, Volume 7, Issue XI, Pages:607-612, November/2018.
  17. “Multi Exposure Fusion of Images through Gaussian Filtering and Principal Component Analysis” published in International Journal of Engineering Research and Advanced Technology (IJERAT), E-ISSN:2454-6135, Volume.4, Issue 8, Pages:37-46, DOI: http://doi.org/10.31695/IJERAT.2018.3296, August -2018.
  18. “Improving the Estimation of Channel Using Virtual Pilot Signals in Wireless Communication Systems” published in International Journal of Modern Electronics and Communication Engineering (IJMECE) ISSN: 2321-2152, Volume No. 5, Issue No.6, Pages:25-29, November, 2017.
  19. “Improving the Estimation of Channel Using Virtual Pilot Signals in Wireless Communication Systems” published in International Journal of Modern Electronics and Communication Engineering (IJMECE) ISSN: 2321-2152, Volume No. 5, Issue No.6, Pages:30-35, November, 2017.
  20. “A Novel Code Compression for Embedded Systems Using Reversible Logic Gates” published in International Journal of Scientific Research in Computer Science, Engineering and Information Technology (IJSRCSEIT), ISSN: 2456-3307, Volume 2, Issue 5, Pages:960-964, UGC Approved Journal [ Journal No: 64718], September-October-2017.
  21. “Improvement of a Doppler Profile of a Lower Atmospheric Wind Profiler Radar Time Series Data Using Signal Processing Techniques” in International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 22, Pages:11780-11786, 2017.
  22. “A Novel Approach to Improve the Quality of Service for the MAC Spectrum in Wireless Networks” published in International Journal of Computer Networks and Wireless Communications (IJCNWC), ISSN: 2250-3501, Vol.7, No 5, Pages:36-42, Sep-Oct 2017.
  23. “Design A Quality of Service Based Multihop Network Architecture Integrating Cognitive Radio Adhoc Networks” International Journal of Advance Engineering and Research Development (IJAERD), ISSN (P): 2348-6406 Volume 4, Issue 8, Pages:719-726, August -2017.
  24. “An Investigation on Interference Reduction Techniques in Cellular and Wireless Communication” in IPASJ International Journal of Electronics & Communication (IIJEC), ISSN: 2321:5984, Volume 5, Issue 4, Page No.1-12, April 2017.
  25. “Channel Optimisation and Interference Mitigation Techniques for Advanced Cellular Mobile Communication” in International Journal for Research in Applied Science & Engineering Technology (IJRASET), ISSN: 2321-9653, Volume 5 Issue XI, Pages: 1326-33, November 2017.
  26. “Fading Mitigation Techniques in Wireless Mobile Communication Systems” in International Journal of Engineering Technology Science and Research (IJETSR), ISSN 2394 – 3386 Volume 4, Issue 5, Pages:782-792, May 2017.
  27. “Detecting and Correcting Multiple Bit Upsets using Erasure Codes for Protecting SRAM Based FPGAs” in International Journal of VLSI System Design and Communication systems ISSN 2322-0929 Vol.04, Issue.10, October-2016, Pages:011-0916.
  28. “IOT Based Weather Informative System” in International Journal of Advanced Information Science and Technology (IJAIST) ISSN: 2319:2682 Vol.53, No.53, September 2016 DOI: 10.15693/IJAIST/2016.v53i53.ORCID:0000-0002-9613-1149, Researcher ID: K-5627-2016, Page No.13-17.
  29. “Constructing the Blue Print of Rapid Reverse Converter through the Parallel Prefix Adder” in International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.05, Issue.35 October-2016, Pages:8289-8293.
  30. “Delay-Aware Wi-Fi Offloading and Network Selection” in International Journal of VLSI System Design and Communication systems ISSN 2322-0929 Vol.04, Issue.08, August-2016, Pages:0566-0571.
  31. “An Analytical Performance for Multi-Antenna Cognitive Radio Network (CRN) Systems” in International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.05, Issue.19 July-2016, Pages:3970-3975.
  32. “Virtual Pilot Signals For MIMO-OFDM Systems for Iterative Channel Estimation” In Anveshana’s International Journal Of Emerging Trends In Electronics Technology, Software Engineering And Computational Intelligence ISSN:2455:6300 Volume 1, Issue 1, Sept/Oct- 2016, Page No.20-25.
  33. “A Novel Design Algorithm for Low Complexity Programmable FIR Filters by Using Extended Double Base Number System” in International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.05, Issue.35 October-2016, Pages:7309-7312.
  34. “Delay-Aware Wi-Fi Offloading and Network Selection” In Anveshana’s International Journal of Emerging Trends in Electronics Technology, Software Engineering and Computational Intelligence ISSN:2455:6300 Volume 1, Issue 1, Sept/Oct- 2016, Pages.12-19.
  35. “Low Power Modeling of Topologically Compressed Static Flipflop” in International Journal of Engineering and Computer Science (IJECS) ISSN: 2319-7242 Volume 4 Issue 6 June 2015, Page No. 12293-12297.
  36. “VLSI Modeling of Sensitization Input Vector Effect on Propagation Delay For 32 Nm CMOS Designs” is published in “International Journal of VLSI and Embedded Systems-IJVES”, (ISSN: 2249 – 6556) Volume 06, Article 05583; May 2015.
  37. “Optimized Design and Implementation of Ieee-754 Floating Point Processor” Published in International Journal of Research (IJR), Vol-2, Issue-05 May 2015. ISSN: 2348-6848 With Impact Factor 3.541(Open Access Online and Print Version) pages 798-806.
  38. “VLSI Design of Low Energy Modeling for Network on Chip (NOC) Applications” is published in “International Journal of VLSI and Embedded Systems-IJVES”, (ISSN: 2249 – 6556) Volume 06, Article 06596; June 2015.
  39. “VLSI Hardware Modeling of Dynamic RNS Structure for High-end Computations” is published in “International Journal of VLSI and Embedded Systems-IJVES”, (ISSN: 2249 – 6556) Volume 06, Article 06597; June 2015.
  40. “VLSI Modeling Side Channel attaches on Modern Cache Based Processors” Published in International Journal of Research (IJR), Vol-2, Issue-05 May 2015. ISSN: 2348-6848 With Impact Factor 3.541(Open Access Online and Print Version) pages 1099-1102.
  41. “Hardware Modeling of sorting Mechanism for finding first Maxima/Minima Values for a set Greater than 2” Published in International Journal of Research (IJR), Vol-2, Issue-05 May 2015. ISSN: 2348-6848 With Impact Factor 3.541(Open Access Online and Print Version) pages 662-668.
  42. “VLSI Modeling of Efficient Carry Select Adder with Redundant Encoding Technique” Published in International Journal of Research (IJR), Vol-2, Issue-05 May 2015. ISSN: 2348-6848 With Impact Factor 3.541(Open Access Online and Print Version pages 657-662. “Computations of Elementary Functions Based on Table Lookup and Interpolation” in the International Journal of Engineering
  43. Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages1-7.
  44. “VLSI Modeling of High Speed Dedicated Short Range Communication Application Systems” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages36-40.
  45. “DFE FOR CDMA SYSTEMS OVER FADING CHANNEL USING QPSK SIGNALING SCHEM” in the International Journal of Research in Electronics (IJRE), Volume01, Issue 03 Year 2014, ISSN No:  2349-252X, Page no: 1-5.
  46. “Implementation of Multi Mode AES Algorithm Using Verilog” in International Journal of Engineering research (IJER)ISSN: 2319-6890(online), 2347-5013(print) Volume No.3, Issue No.12, pp: 780-785, 01 Dec. 2014.
  47. “VLSI DESIGN OF LOW ENERGY MODELING FOR NETWORK ON CHIP (NoC) APPLICATIONS” published in i-manager’s Journal on Electronics Engineering, Print ISSN: 2229-7286, E-ISSN: 2249-0760, 5 · No. 1 · September – November 2014, Pages 27-32.
  48. “Efficient Sorting Mechanism for Finding First W Maximum/Minimum Values By Using B.W.A Architecture” published in i-manager’s Journal on Embedded Systems, Vol. 3 3, August – October 2014 Pages 39-44.
  49. “Optimizing Data Encoding Schemes to Reducing Energy Consumption in Network on Chip” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages8-14.
  50. “Static Power Reduction Using Reconfigurable Multi-Mode Switches” in IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 6, Ver. III (Nov – Dec. 2014), PP 25-31 e-ISSN: 2319 – 4200, p-ISSN No.: 2319 – 4197.
  51. “Power Risky Pattern Reduction by Launch on Capture and Weighted Switching Activity for At Speed Scan Based Testing” in the International Journal of Science and Engineering (IJSE) ISSN: 2347-2200, Volume-2, Number-2, July-Dec-2014, Pages 81-90.
  52. “A New Compensation Technique for Stable the Gain of Sub-Micron Amplifiers”in the International Journal of Engineering research (IJER)ISSN: 2319-6890(online), 2347-5013(print) Volume No.3, Issue No.12, pp: 786-790 01 Dec. 2014.
  53. “Efficient Hardware Implementation for Advanced Encryption Standard With 256 Bit Key Lengths” in the International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.03, Issue, 18 August-2014, Pages: 3873-3877.
  54. “Implementation Of Decimal Matrix Code For Correcting Cell Upsets In Static Random Access Memories” in the International Journal of Electrical, Electronics and Data Communication (IJEEDC), ISSN: 2320-2084 Volume-2, Issue-10, Oct.2014, Pages 72-76.
  55. “Design Of Reduced Power Flip Flop Based On Signal Feed Through Scheme” in the International Journal of Science and Engineering (IJSE) ISSN:2347-2200, Volume-2 , Number-2, July-Dec-2014, Pages 72-80.
  56. “On Chip Generation Of Function Test For High Transition Faults Using Fixed Hardware” in the International Journal of Electrical, Electronics and Data Communication (IJEEDC), ISSN: 2320-2084 Volume-2, Issue-10, Oct.2014, Pages 77-81.
  57. “Implementation of Multi-Bit flip-flop for Power Reduction in CMOS Technologies” in the International Journal of Innovative Research in Computer and Communication Engineering (IJIRCCE) ISSN (Online): 2320-9801, ISSN (Print): 2320-9798, 2, Special Issue 4, September 2014, Pages: 91-98.
  58. “Power Safe Test Pattern Refinement for Transition Fault Coverage for Speed Scan Based Testing” in the International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.03, Issue.20 September-2014, Pages: 4099-4105.
  59. “Pipelined Routing Network for Multiprocessor System on Chip” in the International Journal of Advanced Computational Engineering and Networking (IJACEN), ISSN: 2320-2106. Volume-2 Issue-10, Oct-2014 PAGES 1-5.
  60. “Implementation of Fixed Angle Rotation using Bi-Rotational CORDIC” in the International Journal of Scientific Engineering and Technology Research (IJSETR) ISSN 2319-8885, Vol.03, Issue.20 September-2014, Pages: 4056-4061.
  61. “An Investigation on Different Data Types Passing Through OFDM Technique by Using QPSK Modulator” in the International Journal of Computer Applications in Engineering, Technology and Sciences (IJ-CA-ETS), ISSN: 0974-3596 | April 2013- Sept 2013 |   Volume 5: Issue 2.
  62. “A Review of Issues, Application and Opportunities in Indoor Wireless Optical Communication Systems” in “Role of Physics in Sustainable Development – RPSD2013” in the Indian Streams Research journal (ISRJ) ISSN: -2230-7850.
  63. “Novel Practice of Combating Design Challenges Using Special Cells”, in the International Journal of Emerging Trends & Applications in Engineering Technology and Sciences (IJ-ETA-ETS) ISSN 0974-3588, Volume 5, Issue1, JAN’ 12 – JUNE’ ’12, 2012.
  64. “Protocol Routing in Ad-hoc Sensor Networks” in the International Journal of Science and Technology (IJST) ISSN (Online):2250-141X, Volume 2 Issue 1, Feb.2012, Pages 13-21.
  65. “Field Programmable Gate Array (FPGA) Implementation of Universal Modulator Using Co-Ordinate Rotation Digital Computer (CORDIC) Algorithm” in the International Journal of Computer Applications in Engineering Technology and Sciences (IJ-CA-ETS): ISSN 0974-3596  volume 4 Issue-1, Oct,2011-Mar 20112, Pages 129-135.
  66. “Reduction of Co Channel Interference in Cellular Systems” in the International Journal of Science and Technology (IJST) ISSN (Online):2250-141X, Volume 1 Issue 1, Nov.2011, Pages45-49.
  67. “Analysis of Non-Coherent Receiver for joint timing recovery and Data detection in DS-CDMA Systems “in the International Journal of Computer Applications in Engineering Technology and Sciences (IJ-CA-ETS): ISSN 0974-3596  volume 4 Issue-2, April2012-September2012, Page 069-076.
  68. “VLSI Modeling of Side Channel Attacks on Modern Processors” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages20-25.
  69. “32nm Based High-Speed Low Calibrated Flash ADC comparator with improved ENOB” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages15-19.
  70. “Reducing the delay in conventional CSLA by using parallel path carry propagation SQRT CSLA Technique” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages26-30.
  71. “Ultra Low Power Based TCFF in 40nm CMOS Technology” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages41-49.
  72. “Efficient Sorting Mechanism for Finding First W Maximum/Minimum Values by Using B.W.A Architecture” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium On Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages50-55.
  73. “Design for Arithmetic Based Dynamic Binary-To-RNS Conversion Using Multi modulo Operations” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages56-61.
  74. “Optimized Design and implementation of IEEE-754 Floating point processor” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages62-67.
  75. “Analysis of Nanometer CMOS ICS on Propagation Delay” in the International Journal of Engineering Research and Applications (IJERA) National Level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S- 13th & 14th March 2015) ISSN: 2248-9622, Pages68-74.

Conferences

  1. International Conference on Intelligent Computing and Control Systems (ICICCS 2017) held at Vaigai College of Engineering during June 15-16, 2017 at Madurai, presented a manuscript titled as “Device-to-Device Communications in Long Term Evaluation-Advanced Network”, 978-1-5386-2745-7/17/$31.00 ©2017 IEEE, pages:818-823.
  2. 3rd International Conference on Research Trends in Engineering, Applied Science and Management (ICRTESM-2017) at Institution of Electronics and Telecommunication Engineers, (IETE) , Erandwane, Pune, Maharashtra, India, on 28th May 2017 , presented a manuscript titled as “Fading Mitigation Techniques in Wireless Mobile Communication Systems” ISBN: 978-81- 934083-1-5, Pages:667-677.
  3. International Conference on Emerging Trends in Basic Sciences, Engineering Technologies And Management Sciences(ICETBSETMS-2016) held at Hotel Bliss, Tirupathi on 23rd July, 2016 presented a paper titled as “Delay Aware Wi-Fi Offloading and Network Selection” Organized by Anveshana Educational And Research Foundation In Association With Shri JJT University, Jhunjhunu, Rajasthan, Paper Id: ECE 1022, pages35-36.
  4. International Conference on Emerging Trends in Basic Sciences, Engineering Technologies And Management Sciences (ICETBSETMS-2016) held at Hotel Bliss, Tirupathi on 23rd July, 2016 presented a paper titled as “An Analytical PERFORMANCE FOR MULTI-ANTENNA COGNITIVE RADIO NETWORK (CRN) Systems” Organized by Anveshana Educational And Research Foundation In Association With Shri JJT University, Jhunjhunu, Rajasthan, Paper Id: ECE 1030, pages44.
  5. International Conference on Developments in Engineering Research (ICDER-2015) held at Hotel Chennai gateway, Chennai on 17th May, 2015 presented a manuscript titled as “By Using Parallel Path Carry Propagation Technique Reducing The Delay in CSLA” ISBN:978-1511884-098 pages 107-111.
  6. International Conference on Emerging Trends in Basic Sciences, Engineering Technologies And Management Sciences(ICETBSETMS-2016) held at Hotel Bliss, Tirupathi on 23rd July, 2016 presented a paper titled as “Virtual Pilot Signals For MIMO-OFDM Systems For Iterative Channel Estimation” Organized by Anveshana Educational And Research Foundation In Association With Shri JJT University, Jhunjhunu, Rajasthan, Paper Id: ECE 1027, page 41.
  7. International Conference on Emerging Trends in Basic Sciences, Engineering Technologies And Management Sciences (ICETBSETMS-2016) held at Hotel Bliss, Tirupathi on 23rd July, 2016 presented a paper titled as “Constructing The Blue Print Of Rapid Reverse Converter Through The Parallel Prefix Adder” Organized by Anveshana Educational And Research Foundation In Association With Shri JJT University, Jhunjhunu, Rajasthan, Paper Id: ECE 1047, page 61.
  8. International Conference on Developments in Engineering Research (ICDER-2015) held at Hotel Chennai gateway, Chennai on 17th May, 2015 presented a manuscript titled as “Optimized Sorting Mechanism for Finding First Wm Maxima/Minima Values from A Set Greater Than 2 By Using B.W.A Architecture” ISBN:978-1511884-098. Pages 127-134.
  9. International Conference on Developments in Engineering Research (ICDER-2015) held at Hotel Chennai gateway, Chennai on 17th May, 2015 presented a manuscript titled as “VLSI Design of Low Energy Modeling for Network on Chip (NOC) Applications” ISBN:978-1511884-098. Pages 122-126.
  10. International Conference on Emerging Trends in Basic Sciences, Engineering Technologies And Management Sciences(ICETBSETMS-2016) held at Hotel Bliss, Tirupathi on 23rd July, 2016 presented a paper titled as “Virtual Pilot Signals For MIMO-OFDM Systems For Iterative Channel Estimation ” Organized by Anveshana Educational And Research Foundation In Association With Shri JJT University, Jhunjhunu, Rajasthan, pages41
  11. 3rd International Conference on Innovations in Electronics and Communication Engineering (ICIECE-2014) at Guru Nanak Institutions, Hyderabad held on18th & 19th July, 2014 presented a paper titled as “Design of Reduced Power Flip Flop Based on Signal Feed through Scheme”.
  12. Eleventh IRF International Conference on Electrical & Electronics Engineering (IACEEE)held at Chennai on 17th August 2014, Chennai, India, presented a Paper Titled as” Pipelined Routing Network for Multiprocessor Network On Chip “ISBN: 978-93-84209-47-6.
  13. 3rd International Conference on Innovations in Electronics and Communication Engineering (ICIECE-2014) at Guru Nanak Institutions, Hyderabad held on18th & 19th July,2014 presented a paper titled as “Process Variation Compensation Technique for Submicron CMOS”.
  14. 1st International Conference on Innovations in Electrical & Electronics Engineering (ICIEEE-2014) held at Guru Nanak Institutions, Hyderabad on September 5th & 6th , 2014 presented a Paper Titled “On Chip Generation of Functional Tests for High Transition Faults Using Fixed hardware” Pages 112-115 in ISBN :978-93-82163-55-8.
  15. 1st International Conference on Innovations in Electrical & Electronics Engineering (ICIEEE-2014) held at Guru Nanak Institutions, Hyderabad on September 5th & 6th, 2014 presented a Paper Titled “Power Safe Test Pattern Refinement for Transition Fault Coverage for Speed Scan based testing” Pages 116-120 in ISBN: 978-93-82163-55-8.
  16. 1st International Conference on Innovations in Electrical & Electronics Engineering (ICIEEE-2014) held at Guru Nanak Institutions, Hyderabad on September 5th & 6th, 2014 presented a Paper Titled “Implementation of Decimal Matrix Code for Correcting Cell Upsets in Static Random-Access Memories”.
  17. International conference on Advances in Communication, Navigation & Computer Networks (ACNCN-2012) held on 17th & 18th March 2012, presented a paper entitled as” Analysis of Non-Coherent Receiver For Joint Timing Recovery And Data Detection In DS-CDMA Systems”.
  18. Inter National Conference on Emerging Trends in Signal Processing and VLSI Design held on June 11-13th, 2010 presented a paper titled “Optimizations of Ad Hoc Interconnected Mobile Networks”.
  19. International Conference on Innovations in Electronics and Communication Engineering (ICIECE-2014) held on18th & 19th July,2014 at Guru Nanak Institutions, Hyderabad presented a paper titled as “High Secure Hardware Implementation for Advanced Encryption Standard”.
  20. National Conference on emerging trends in data mining, ware housing and computer communication held on June 29-30, 2009 presented a paper on “Ad Hoc Interconnected Mobile Networks”.
  21. 4th National Level Conference (EPSCCON’14) at VELTECH University, Department of ECE and EEE held on 26th August 2014 Presented a Paper titled as “Implementation of Fixed Angle Rotation using Bi-Rotational CORDIC”.
  22. National Conference on Role of IQAC-Sustenance and Enhancement of Quality in HEIs NACC Sponsored & Organized by Internal Quality Assurance Cell at St Joseph’s Degree & PG College, King Koti, Hyderabad held on September 25-26th September, 2012 presented a paper on “Quality enhancement through Teaching-Learning Process and academic Linkages”.
  23. National Seminar on Emerging Trends in Commerce- An Edge, held on 19th December 2013 presented a paper titled “Tracking Devices for Visually impaired & Elderly Care System by Using GPS and RFID Tags- an Enhanced scope for Indian Retail”.
  24. 4th National Level Conference (EPSCCON’14) at VELTECH University held on 26th August 2014 Presented a Paper titled as “High Secure Hardware Implementation for Advanced Encryption Standard”.
  25. National Conference on “VLSI Design, Architecture and Applications” organized by the School of Electronics (SENSE), VIT University, Chennai Campus held on 18th April 2014. Presented a Paper on “Design of Reduced Flip-flop Based on Signal Feed Through Scheme”.
  26. National Conference on Recent Trends in Electronics & Computer Science Engineering (NCRTECE-2K14) at SV College of Engineering, Tirupathi on 27th August 2014 Presented a Paper Titled “Implementation of Multibit Flip-Flop For Power reduction in CMOS Technique”.
  27. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “VLSI Modeling of High Speed Dedicated Short Range Communication Application Systems”.
  28. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “32nm Based High-Speed Low Calibrated Flash ADC Comparator with Improved ENOB”.
  29. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March, 2015 presented a paper Titled “Reducing the Delay in Conventional Csla By Using Parallel Path Carry Propagation Sqrt CSLA Technic”.
  30. 2nd National Conference on Innovative & Emerging Trends in Engineering and Technology (NCIETET’15) organized by Panimalar Institute of Technology, Chennai held on 14th May,2015 Presented a paper on “VLSI Design of Low Power-High Speed fmo/Manchester Encoders for DSRC Systems” page50, ISBN: 978-93-81208-52-6.
  31. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “Ultra Low Power Based TCFF In 40nm CMOS Technology”.
  32. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “Design for Arithmetic Based Dynamic Binary-To-RNS-Conversion Using Multi Modulo Operations”.
  33. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “Optimized Design and Implementation Of IEEE-754 Floating Point Processor”.
  34. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “Optimizing Data Encoding Schemes to Reducing Energy Consumption In Network On Chip”.
  35. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “Efficient Sorting Mechanism For Finding First W Maximum/Minimum Values By Using B.W.A Architecture”.
  36. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “VLSI Modeling of Advanced Cryptographic Units with Montgomery Modular Technique”.
  37. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “Analysis Of Nanometer CMOS ICS On Propagation Delay”.
  38. National level Technical Symposium on Emerging Trends in Engineering & Sciences (NLTSETE&S) at CR Engineering College, Tirupathi on 13th & 14th March,2015 Presented a paper Titled “Computations Of Elementary Functions Based On Table Lookup And Interpolation”.

 

Funded Projects

S. No Project Description Name of the Funding Agency Funds Grated Year Duration
1 Seminar Grant SERB, DST 1,00,000/- 2016  

 

Professional Membership Details: –

  1. Life member in Indian Society of Technical Education (ISTE).
  2. Life Member in Institute of Electronics & Telecommunication Engineers (MIETE), New Delhi.
  3. Member in International Association of Engineers (IAENG) M.Id.106514.
  4. Member in Institution of Electrical and Electronics Engineer (IEEE) M.Id.94136197
  5. Fellow Member in International Society for Research and Development (FISRD)
  6. Editorial Board Member in International Journal of Innovative, Science, Engineering & Technology (IJISET) , ISSN 2348-7968.
  7. Scientific Council Member of the International Association of Engineering & Technology for Skill development (IAETSD) Membership No. IAETSD14001200.
  8. Senior member of the International Association of Computer Science and Information Technology (IACSIT) Mem.No. 80349817.
  9. Reviewer for (IJTEEE) International Journal of Technology Enhancements and Emerging Engineering Research (ISSN 2347-4289).

Subjects Taught

Books Published

Brochure