Designation | Assistant Professor |
Years of Experience | 6 Years |
Department | ECE |
Email Id | pulkit@mlrinstitutions.ac.in |
JNTUH Unique Id | 7623-221011-222249 |
Areas of Specialization | Cryptography, Hardware Security, Lightweight Cryptography |
UG Degree | B.E. in Electronics and Communication Engineering (LNCT Bhopal/ RGPV Bhopal), 2009 |
PG Degree | M.Tech in Microelectronics and VLSI Design (NIT Allahabad), 2012 |
Ph.D | Cryptography and VLSI Design (NIT Raipur), 2023 |
Joining Date | 10/10/2022 |
Nature of Association | Regular |
SCI/SCIE Indexed Journals:
1. Pulkit Singh, Bhaskar Agrawal, Bibhudendra Acharya, and Rahul Kumar Chaurasiya, “Low-area and High-speed Hardware Architectures of KLEIN Lightweight Block Cipher for Image Encryption”, Journal of Electronic Imaging, vol. 32, no. 1, pp. 013012, 2023. DOI: 10.1117/1.JEI.32.1.013012
2. Pulkit Singh, K.A.K. Patro, B. Acharya, and R. K. Chaurasiya, “Efficient hardware architectures of Lilliput lightweight algorithm for image encryption,” International Journal of Ad Hoc and Ubiquitous Computing, vol. 41, no. 4, pp. 205–220, 2022. DOI:10.1504/IJAHUC.2022.10051162
3. Pulkit Singh, B. Acharya, and R. K. Chaurasiya, “Low-area and high-speed hardware architectures of LBlock cipher for Internet of Things image encryption,” Journal of Electronic Imaging, vol. 31, no. 3, pp. 033012, 2022. DOI: 10.1117/1.JEI.31.3.033012
4. Pulkit Singh, B. Acharya, and R. K. Chaurasiya, “Modelling and optimisation of high-speed KLEIN architectures on FPGA and ASIC platforms for IoT applications”, International Journal of Ad Hoc and Ubiquitous Computing, vol. 42, no. 4, pp. 207-225, 2023. DOI: 10.1504/IJAHUC.2023.10055684
5. Pulkit Singh, KAK Patro, B. Acharya, and R. K. Chaurasiya, “Hardware-software Co-design Framework of Lightweight CLEFIA Cipher for IoT Image Encryption”, Journal of the Indian Academy of Sciences, SADHANA, vol. 47, no. 213, pp. 1-7, 2022. DOI:10.1007/s12046-022-01994-0
6. K. P. Raja, Z. Mishra, Pulkit Singh, and B. Acharya, “Efficient Hardware Implementations of Lightweight Simeck Cipher for Resource-constrained Applications,” Integration, vol. 88, pp. 343-352, 2022. DOI: 10.1016/j.vlsi.2022.10.009
7. A. Kumar, Pulkit Singh, K.A.K. Patro, and B. Acharya, “High-throughput and area-efficient architectures for image encryption using PRINCE cipher,” Integration, vol. 90, pp. 224-235, 2023. DOI: 10.1016/j.vlsi.2023.01.011
8. M. Kumari, Pulkit Singh, and B. Acharya, “Secure Image Encryption using High throughput Architectures of PRINT Cipher for RFID Applications,” Journal of Electronic Imaging, vol. 31, no. 3, pp. 063036, 2022. DOI: 10.1117/1.JEI.31.6.063036
9. K.P. Raja, Pulkit Singh, Z. Mishra, and B. Acharya, “Efficient area and throughput implementations of lightweight Simeck cipher for resource-constrained applications,” International Journal of Ad Hoc and Ubiquitous Computing, vol. 43, no. 3, pp. 170–182, 2023. DOI: 10.1504/IJAHUC.2023.131776
Scopus Indexed Journals:
1. Pulkit Singh, B. Acharya, and R. K. Chaurasiya, “A comparative survey on lightweight block ciphers for resource constrained applications,” International Journal of High Performance Systems Architecture, vol. 8, no. 4, pp. 250–270, 2019. DOI: 10.1504/IJHPSA.2019.104953
2. P. Modi, Pulkit Singh, and B. Acharya, “Effective hardware architectures for LED and PRESENT ciphers for resource-constrained applications,” International Journal of High Performance Systems Architecture, vol.10, no. 2, pp. 89-104, 2021. DOI: 10.1504/IJHPSA.2021.119151
3. N. Shrivastava, Pulkit Singh, and B. Acharya, “Efficient hardware implementations of QTL cipher for RFID applications,” International Journal of High Performance Systems Architecture, vol. 9, no. 1, pp. 1-10, 2020. DOI:10.1504/IJHPSA.2020.107173
4. R. Gandu, Z. Mishra, Pulkit Singh, and B. Acharya, “Performance optimised architectures of Piccolo block cipher for low resource IoT applications,” International Journal of High Performance Systems Architecture, vol. 9, no. 1, pp. 49-57, 2020. DOI: 10.1504/IJHPSA.2020.107175
Patent:
1.The Commissioner of Patents has granted the patent titled Flexible and Dynamic Key-dependent architecture of KLEIN Block Cipher for IoT Applications, on 18th August 2021, with Patent number: 2021105784, Australian Government, Grant date: 18th August 2021 (Valid up to eight years).
Conferences:
1. Pulkit Singh, B. Acharya, and R. K. Chaurasiya, “Efficient VLSI Architectures of LILLIPUT Block Cipher for Resource-constrained RFID Devices,” In 2019 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2019, pp. 1–6. DOI: 10.1109/CONECCT47791.2019.9012869
2. Pulkit Singh, B. Acharya, and R. K. Chaurasiya, “Pipelined Architectures of LILLIPUT Block Cipher for RFID Logistic Applications,” In 2019 International Conference on Computing, Communication, and Intelligent Systems (ICCCIS), 2019, pp. 452–457. DOI: 10.1109/ICCCIS48478.2019.8974530
3. Pulkit Singh, B. Acharya, and R. K. Chaurasiya, “High Throughput Architecture for KLEIN Block Cipher in FPGA,” In 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), 2019, pp. 64–69. DOI: 10.1109/IEMECONX.2019.8877021
4. Pulkit Singh, P. Modi, B. Acharya, and R. K. Chaurasiya, “Energy-Efficient and High-throughput Implementations of Lightweight Block Cipher,” in International Journal of Innovative Technology and Exploring Engineering, 2019, vol. 9, no. 2S, pp. 35–41. DOI: 10.35940/ijitee.b1022.1292s19
5. P. Modi, Pulkit Singh, B. Acharya, and S. Verma, “High Throughput Pipelined Architecture for AES Cipher,” In Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems, pp. 351-359. Springer, Singapore, 2021. DOI: 10.1007/978-981-16-0275-7_29
6. P. Modi, Pulkit Singh, and B. Acharya, “Multiplexer-based High-speed S-box Architecture for PRESENT Cipher in FPGA,” In Proceeding of Fifth International Conference on Nanoelectronics, Circuits and Communication Systems, pp. 643-652. Springer, Singapore, 2020. DOI: 10.1007/978-981-15-7486-3_55
7. N. Ayesha, Pulkit Singh, and B. Acharya, “An Area-Optimized Architecture for LiCi Cipher,” In Proceeding of 4th International Conference on Nanoelectronics, Circuits and Communication Systems, pp. 157-167. Springer, Singapore, 2020. DOI: 10.1007/978-981-15-2854-5_16
8. N. Shrivastava, Pulkit Singh, and B. Acharya, “A Novel Hardware Architecture for Rectangle Block Cipher,” In Proceeding of 4th International Conference on Nanoelectronics, Circuits and Communication Systems, pp. 169-181. Springer, Singapore, 2020. DOI: 10.1007/978-981-15-2854-5_17
1. Digital Electronics and Computer Organization,
2. Principle of Communication,
3. Digital System Design,
4. Electronic Devices and Applications,
5. Network Security and Cryptography
1. Pulkit Singh, B. Acharya, and R. K. Chaurasiya, “Lightweight cryptographic algorithms for resource-constrained IoT devices and sensor networks,” In Security and Privacy Issues in IoT Devices and Sensor Networks, Academic Press, 2021, pp. 153–185. DOI: https://doi.org/10.1016/B978-0-12-821255-4.00008-0, ISBN: 978-0-12-821255-4. (Elsevier)